What is MIPS?

Microprocessor without Interlocked Pipeline Stages

An example of RISC design

Simplicity favors regularity

add a, b, c # a = b + c
sub x, y, z # z = y - z

Smaller is faster

Registers: fast temporary storage

Saved: $s0 - $s7 (or $16 - $23)

Temporary: $t0 - $t7(or $8 - $15)

Zero: $zero(or $0)

Make the common case fast

lw #load word
sw #save word

la #load address

Memory: Base address, offset

offset(base)

lw $t0, 32($s0)

add $t0, $s1, $t0

sq $t0, 48($s0)

$s0 is the base address, 32 and 48 is the offset

Big-Endian: end of word matches big address

Little-Endian: end of the word matches little address

addi $t0, $s1, 8
addi $t0, $t0, -1

add $t2, $s1, $zero
addi $t0, $zero, 5

addi means add immediate(constant)